DSM DAC

Density Signals and Delta-Sigma Modulation, Part I

Recently I’ve been quite taken by the idea of density signals.  These are similar to digital signals, but are instead represented by a single bit for any given point in time.  A very common example of this is the output of a pulse-width modulator (PWM), which may drive an RC low-pass filter to create a simple digital to analog converter (DAC), facilitate some motor control, etc.  PWMs are commonly made with a single counter with a compare.  The continually counting counter’s compare output will be high during a given pulse width based on the compare result, and thus give the desired duty cycle.  Let’s say we want to create a DAC from this PWM.  We can do this as described above, by tying a resistor and capacitor to the output to create a low-pass filter.  The capacitor will act as the energy storage for the DAC, and the PWM’s duty cycle will define the output voltage of the DAC, assuming a sufficiently quick period for PWM.  The diagram below demonstrates this configuration.

 

Very simply, the counter produces a signal of sufficiently high frequency such that the filter output is effectively a DC representation of the duty cycle described by the following equation.

 

This is pretty cool and all, and allows us to create a decent DAC.  We can create analog signals using this PWM by changing the compare value in time, at a rate of at most once per counter period.  Again, this is called pulse width modulation, and it allows us to convert a digital signal – the one that controls the counter compare value – into a density signal, a string of bits whose duty cycle (or density!) describes its amplitude.  This conversion is between a single, quantized value and a string of bits representing this value is called modulation.  So, what is this delta-sigma modulation, and why is it so cool? Well, let’s look at a different way to make this DAC as s demonstration.

Let’s say that, instead of using a counter with a compare, we instead use an adder and a register to create our density signal.  This is done by registering the adder output and feeding it back into one of its inputs, and taking our digital duty cycle value (as a fraction of the adder width) and feeding it into the other adder input.  The overflow output of the adder will be our density stream output.  This whole circuit is shown in the following diagram.

 

Ok, so what does this do?  Let’s look at a simple example: we will use a common 8-bit adder, and we will use a duty cycle of 50%.  To do this, we place 128 in the duty cycle register, which causes the adder to overflow every other operation.  For a duty cycle of 25%, we use 256/4 = 64, which causes the adder to overflow every 4 operations.  For a duty cycle of 75%, we use 256*3/4 = 192, which causes the adder to overflow 3 out of every four operations.  Why is this desirable?  Because it moves the modulation frequency as high as possible for each given duty cycle, ensuring that digital feed-through at the filter output is minimized, giving you a maximally smooth output.  This modulation scheme is called Delta-Sigma Modulation (DSM).  It is useful for DAC creation, but is particularly useful in analog to digital converters (ADCs), as I will discuss in a later blog post.

To test these claims, I’ve created a couple simple python classes for the PWM and DSM, and tested them with a modulation period of 256 and a duty cycle of 1/8.  The time domain results are as expected, with the PWM producing a single high and single low pulse for each period, and the DSM producing many high and low pulses, as frequently as possible for this decimation period, as shown in the below plots.

Of particular interest is the resulting frequency spectrum, though.  We can see in the below diagram that the PWM has many more low-frequency components, which are much more likely to get through the RC low-pass filter in our DAC.  The DSM, on the other hand, has its energy in much higher frequencies, which are much less likely to bleed through the low-pass filter.  We see this in the figure below.

DSM DACs are pretty cool, but DSM ADCs are much more impressive, and as the embedded world grows to embrace them, understanding them will be integral in utilizing them well.  I will explore these in a future blog post, as well as an exploration of signal processing on density signals.  Thanks for reading!